CMPUT 229 Laboratory Assignment - Pipeline Simulator
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Final Mark:           /100 MARKS TOTAL
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Part 1: _____ /33 Pipeline Stages

Part 2: _____ /7 PreDecode Function

Part 3: _____ /2 Cache Simulation

Part 4: _____ /38 Visual Output

Part 5: _____ /20 Program Style & Commenting

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Part 1: Pipeline Stages

Total: _____ /33

_____ /4 Instruction Fetch (IF)
    * Correct instruction fetched from memory and stored in IF/ID pipeline register.

_____ /8 Instruction Decode (ID)

    _____ /8 ID/EX Latch
        * Correct decoding and storage of control/data signals in ID/EX pipeline register.

_____ /8 Execution (EX)

    _____ /8 EX/MEM Latch
        * Correct values in EX/MEM pipeline register after ALU operations.

_____ /8 Memory Access (MEM)

    _____ /8 MEM/WB Latch
        * Correct values in MEM/WB pipeline register after memory access.

_____ /5 Write Back (WB)

    _____ /5 Register Write
        * Correct values written to destination register (rd).

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Part 2: PreDecode Function

Total: _____ /7

_____ /7 Instruction Breakdown
    * Correct output of the PreDecode function, including rs1, rs2, rd, immediate, and funct3 fields.

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Part 3: Cache Simulation

Total: _____ /2

_____ /2 Hit/Miss Accuracy
    * Correct implementation of cache hit/miss logic, validated via a0 register value and correct X_n+1 value ( placed in X_n )

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Part 4: Visual Output

Total: _____ /38

_____ /20 Pipelining Output
    * Visual output accurately reflects pipeline activity over each cycle.

_____ /13 Register Table
    * Displays correct register values across the timeline of execution.

_____ /5 Simulation Summary
    * Matches expected final state of the simulation.

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Part 5: Program Style & Commenting

Total: _____ /20
Evaluation of code cleanliness, formatting, and documentation.
Deductions include:
- No function headers
- Poor register usage explanation
- Missing or misleading comments
- Bad indentation/formatting
- Unstructured code layout